`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:55:17 04/05/2011
// Design Name:   tree
// Module Name:   C:/Users/Administrator/Desktop/enee408/Wallace_Tree/Tree/four2two_TB.v
// Project Name:  Tree
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: tree
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module four2two_TB;

	// Inputs
	reg [255:0] PP_in;

	// Outputs
	wire [33:0] out_sc;
	wire [33:0] out_ps;

	// Instantiate the Unit Under Test (UUT)
	tree uut (
		.PP_in(PP_in), 
		.out_sc(out_sc), 
		.out_ps(out_ps)
	);

	initial begin
		// Initialize Inputs
		PP_in = 0;

		// Wait 100 ns for global reset to finish
		#100;
        PP_in= 65908;
		  
		// Add stimulus here

	end
      
endmodule

